The present invention relates to the field of programmable devices, and the systems and methods for designing the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to a specific logic operations. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
To provide additional functionality and improve performance, programmable devices often include one or more gate arrays. Each gate array set can be permanently programmed during manufacturing, for example using mask programming techniques, to implement highly-specialized functional blocks. These specialized functional blocks, referred to as hard IP blocks, enable programmable devices to be tailored to specific application segments. For example, hard IP blocks can implement specialized functional blocks used for networking applications, for wireless communications applications, or for signal processing applications. Although hard IP blocks have a fixed configuration set during manufacturing, the remainder of the programmable device may be later programmed and optionally reprogrammed to implement user designs. Thus, programmable device manufacturers can use hard-IP blocks to mass produce programmable devices tailored for specific application segments while still providing their customers with the ability to implement their own user designs.
Typically, hard IP blocks require some memory to perform their intended functions. To meet this need, a programmable device may include a fixed size memory block interfaced directly with the gate array used to implement the hard IP blocks. However, a fixed sized memory block may not be optimal for each of the different hard IP blocks, in terms of the number of memory blocks, memory size, memory type, and memory access ports. Alternatively, memory can be constructed in the gate array itself by configuring portions of the gate array to act as flip-flops. This solution consumes a large amount of area, which either decreases the number of gates available for the hard-IP block or increases the gate array size and hence cost of the programmable device. Another alternative is to include a diffuse set of memory cells in the gate array. However, because the ratio of memory to logic varies between different hard-IP blocks, this alternative defeats the purpose of using the gate array to efficiently implement a variety of different hard IP blocks.
It is therefore desirable for a system and method to enable users to efficiently create memory units for a variety of different hard-IP blocks. It is further desirable that the system and method enable programmable device users to tailor the characteristics of memory units to match the requirements of each hard-IP block. It is further desirable that the memory units be readily integrated with the design and testing processes of hard-IP blocks.